As integrated circuits continue to scale downward in size, the finFET has become an attractive device for use with smaller nodes, e.g., the 22 nm node and beyond. In a finFET, the channel is formed by a semiconductor fin and a gate electrode is located on at least two sides of the fin. Due to the advantageous feature of full depletion in a finFET, the increased number of sides on which the gate electrode controls the channel of the finFET enhances the controllability of the channel in a finFET. The improved control of the channel allows smaller device dimensions with less short channel effects as well as larger electrical current that can be switched at high speeds. A finFET device generally has faster switching times, equivalent or higher current density, and much improved short channel control than planar CMOS technology utilizing similar critical dimensions.
Given the control of the conducting channel by the gate, which “wraps” around the channel, very little current is allowed to leak through the body when the device is in the off state. This allows the use of lower threshold voltages, which results in optimal switching speeds and power. However, the 3D nature of finFETs and the multiple fins making up the transistors introduce a large number of parasitic resistance and capacitances to be considered. For example, gate to contact capacitance degrades device performance if spacers are too thin; whereas, thick spacers degrade device performance due to increased resistance.